1. Field of the Invention
This invention relates generally to an automatic phase control apparatus for use with a time base corrector and more particularly is directed to an automatic phase control apparatus for use with a time base corrector which is suitable for being applied to a video signal processing apparatus used in a video tape recorder (VTR).
2. Description of the Prior Art
In the VTR, for a color framing detecting apparatus, a time base correcting apparatus and the like, it is necessary to establish a predetermined phase relation between a phase of a horizontal synchronizing signal and a phase of a subcarrier produced from a burst signal of a composite video signal. To this end, an automatic phase control (APC) circuit is used. For example, in time base correcting apparatus (TBC), a prior art circuit arrangement as shown in FIG. 1 is used.
In the circuit shown in FIG. 1, a synchronizing signal SYNC is extracted from a reproduced input signal VDIN reproduced from a tape in a synchronizing separating circuit 1, and then supplied to a write clock generating circuit 2. Also, a reproduced burst signal BURST is extracted from the reproduced input signal VDIN in a burst synchronizing separating circuit 3, and then supplied to the write clock signal generating circuit 2.
The write clock signal generating circuit 2 produces a write clock signal WCK and a write start pulse signal WZERO which are synchronized with the synchronizing signal SYNC and the reproduced burst signal BURST and hence contain time basis fluctuations. The write clock signal WCK is supplied to an A/D (analog-to-digital) converting circuit 4 as its sampling signal and also to a memory control circuit 5 together with the write start pulse signal WZERO.
When supplied with the write start pulse signal WZERO, the memory control circuit 5 designates a start address of each scanning line to a memory 6 and then sequentially writes video signal data of one scanning line amount by sequentially incrementing the address of the memory 6 by the write clock signal WCK.
The data written in the memory 6 is read out by a read clock signal RCK and a read start pulse signal RZERO produced from a read clock generating circuit 7 which receives a reference pulse signal REF having a stable period on the basis of the reference pulse signal REF. In other words, when receiving the read start pulse signal RZERO, the memory control circuit 5 designates the start address of the memory area in which the data of each scanning line is stored. Thereafter, the memory control circuit 5 sequentially reads out the video data of 1H (H is the horizontal period) from the memory 6 by sequentially incrementing the address by the read clock signal RCK.
This video signal data is converted to an analog signal by a D/A (digital-to-analog) converting circuit 8 which is driven by the read clock signal RCK and then fed to a phase adjusting circuit 9. The phase adjusting circuit 9 adds the video signal data with a synchronizing signal SYNCX, a burst signal BURSTX and a blanking pulse BLKX that are respectively produced from the read clock generating circuit 7 on the basis of the reference pulse signal REF and delivers the same as a reproduced output signal VDOUT.
In the TBC arranged as shown in FIG. 1, when the video signal data of each scanning line is written in the memory 6, it is necessary that, in order to repeatedly write the start data of the video signal in the memory area having a predetermined start address with good reproducibility, the timing (that is, the phase) at which the memory control circuit 5 produces the start address be automatically adjusted.
Particularly, in order to maintain the continuity of the phase of the color subcarrier in the memory 6 and to easily make the correspondence in the processing at the read side circuit, when the video signal data is written in the memory 6, data corresponding to one period of the color subcarrier must be written as a unit.
For this reason, in the memory control circuit 5, the timing at which it produces the write start pulse signal WZERO must be synchronized with the color subcarrier. However, when a television signal in the NTSC system is processed, the frequency of the color subcarrier is (455/2) times the line frequency so that the phase of the subcarrier at each adjacent scanning line is displaced by 1/2 period. Accordingly, it is necessary to displace the phases of the write start pulse signal WZERO supplied from the write clock generating circuit 2 and the read start pulse signal RZERO transmitted from the read clock generating circuit 7 by 1/2 period (about 140 ns) of the color subcarrier at every line.
As in the writing mode the phase of the write start pulse signal WZERO is displaced by 1/2 period at every horizontal line, the phase of the read start pulse signal RZERO is correspondingly displaced by 1/2 period at every horizontal line similarly in the reading mode, so that the phase relation between the video signal data read out from the memory 6 is recovered completely.
In order to produce the write start pulse signal WZERO and the read start pulse signal RZERO having such phase displacement, in the prior art such an automatic phase control circuit (APC circuit) 11 as shown in FIG. 2 is provided. In FIG. 2, there is shown the write clock generating circuit 2.
In the APC circuit 11, a horizontal synchronizing signal HSYNC contained in the synchronizing signal SYNC supplied from the synchronizing separating circuit 1 (FIG. 1) is applied to a switching input terminal P1 of a switching circuit 12 directly, while it is delayed by a delay circuit 13 and then fed to another switching input terminal P2 of the switching circuit 12. The switching circuit 12 is changed in position to the switching input terminal P1 or P2 at every 1H interval by a line sequential switching signal LAL which changes its logic level at every 1H period on the basis of the reproduced horizontal synchronizing signal HSYNC. Accordingly, the reproduced horizontal synchronizing signal HSYNC is delayed by 1/2 period (about 140 ns) at every 1H interval and then fed to a timer circuit 14 formed as a monostable-multivibrator arrangement as its trigger signal.
The timer circuit 14 produces a timer output MODH indicative of a time point close to the time point at which the write start pulse signal WZERO is to be produced on the basis of the timing of the reproduced horizontal synchronizing signal HSYNC. When the timer circuit 14 receives the reproduced horizontal synchronizing signal HSYNC (FIG. 3B-2) at a time point t.sub.0 from the switching input terminal P1 of the switching circuit 12 with respect to an N-th scanning line LN as shown in FIGS. 3A-2 to 3E-2, the timer circuit 14 produces the timer output MODH which rises to logic "1" which is shown in FIG. 3D-2. Thereafter, the timer circuit 14 operates to change the timer output MODH to logic "0" at a time point just before the time point t.sub.2 at which the write start pulse signal WZERO (FIG. 3E-2) is produced. In the case, it is previously determined that the write start pulse signal WZERO is produced at the zero cross time point t.sup.2 (crossing from the negative side to the positive side) of a predetermined order of a reference burst signal BCOSC (FIG. 3C-2) which is produced from the write clock generating circuit 2 (FIG. 1) on the basis of the reproduced burst signal BURST.
Whereas, with respect to an (N+1)th scanning line L(N+1), the timer circuit 14 receives the reproduced horizontal synchronizing signal HSYNC through the delay circuit 13 and the switching input terminal P2 of the switching circuit 12 as the trigger signal so that as shown in FIG. 3D-1, the timer circuit 14 produces the timer output MODH which rises at a time point delayed from the time point t.sub.0 by the delay time (140 ns) of the delay circuit 13. Thereafter, at a time point near a time point t.sub.4 at which the write start pulse signal WZERO is to be produced, the timer circuit 14 changes the logic level of the timer output MODH to "0". In this case, since the phase of the reference burst signal BCOSC is delayed by 1/2 period (corresponding to the delay time of the delay circuit 13) of the color burst signal as compared with the case of FIG. 3C-2, the falling timing of the timer output MODH of the timer circuit 14 occurs just before the write start pulse signal WREZO in any scanning line.
This timer output MODH is supplied to and compared with the reference burst signal BCOSC by a phase comparing circuit 15. The phase comparing circuit 15 compares the falling edges (FIGS. 3D-2 and 3D-1) of the timer output MODH with the zero cross points of the reference burst signals (FIGS. 3C-2 and 3C-1), produces a phase error output PER indicative of the phase difference and then supplies it to the timer circuit 14 as a measuring time control signal. At that time, the timer circuit 14 is operated such that the phase error output PER indicates a phase difference relative to the phase which is previously determined to be a phase just advanced from the zero cross point of the reference burst signal BCOSC.
The timer output MODH the phase of which is controlled as above is supplied as an input data to a latch circuit 16 that performs the latch operation at the zero cross point of the reference burst signal BCOSC. Then, the latch circuit 16 delivers the write start pulse signal WZERO which falls down to "0" at the time point at which reference burst signal BCOSC crosses the zero cross point. Thus, since the timer output MODH is fallen to logic "0" just before the time point (that is, t.sub.2 and t.sub.4) at which the video signal data of the reproduced input siganl VDIN is started to be written in the memory 6, it is possible to surely produce the write start pulse signal WZERO that is synchronized with the zero cross point of the reference burst signal BCOSC.
In addition to the above-mentioned circuit arrangement, in the APC circuit 11 of FIG. 2, a switching circuit 17 is provided at the output terminal of the phase comparing circuit 15 and a predetermined voltage, for example, an earth voltage is supplied through this switching circuit 17. When the signal level of the phase error output PER exceeds over a lock-in range, the switch 17 is closed by a detecting output of an APC releasing level detecting circuit 18, to thereby return the phase error output PER to the earth voltage.
In this circuit arrangement, since the phase locking loop by the output of the phase comparing circuit 15 is changed over in stable point at every scanning line, there is then a fear that the timer output MODH will not be locked in the phase immediately before the time point t.sup.2 or t.sub.4 of FIG. 3. Further, there is a fear that when the reproduced horizontal synchronizing signal HSYNC is dropped by, for example, dropout or phase jump, the timer output MODH will not be locked in. Accordingly, when the phase error output PER of the phase comparing circuit 15 is fluctuated to the value that can not lock in, this fluctuation is detected by the APC locking level detecting circuit 18 and the phase error output PER is forced to be locked to zero volts through the switching circuit 17 so that the APC operation is returned to the normal operation state. Thus, when the reproduced horizontal synchronizing signal HSYNC is returned to the normal operation state, the timer output MODH of the timer circuit 14 is returned to the nearest stable point (the zero cross point of the reference burst signal BCOSC) so that the phase reproducibility of the write start pulse signal WZERO may be secured.
However, in the circuit arrangement of FIG. 2, if the timer output MODH falls down at the time point at which the trailing edge of the timer output MODH corresponds to the center of the stable point which exists at every period of the reference burst signal BCOSC, there exist two stable points. In practice, when the timer circuits are produced, the counting times thereof inevitably are scattered and hence there is a fear that an inaccurate timer circuit will be used.
In this case, the write start pulse signal WZERO of the single phase can not be produced, so that the APC circuit with such a timer circuit can not be used in editing the reproduced video signal, in which the reproducibiliy of the phase of the video signal is strictly demanded.
To solve this problem, there is proposed a circuit as shown in FIG. 4. In FIG. 4, like parts corresponding to those of FIG. 2 are marked with the same references and will not be described in detail. As shown in FIG. 4, the timer circuit 14 is formed of a first monostable-multivibrator 14A which has a very large count time and a second monostable-multivibrator 14B which has a very small count time that is about one period of, for example, the burst signal. The phase error output PER from the phase comparing circuit 15 is supplied through the buffer circuit 21 to the first monostable-multivibrator 14A as a count time control signal thereof.
Further, the second monostable-multivibrator 14B is provided with a count time adjusting element 14C formed of, for example, a variable resistor, whereby the trailing edge of the timer output MODH can be adjusted delicately by adjusting the count time adjusting element 14C.
In this case, the output terminal of the phase comparing circuit 15 is connected with a phase error output holding capacitor 22 and an OR circuit 23 is connected between the APC releasing level detecting circuit 18 and the switching circuit 17, in which the switching circuit 17 is closed by an adjusting mode signal ADJ through this OR circuit 23.
The timer output MODH and the reference burst signal BCOSC are supplied to a window detecting circuit 25 which lights up a display element 26 when the phase difference therebetween reaches a predetermined window range. The window detecting circuit 25 detects when that the phase of the timer output MODH closely approaches the stable point (that is, any one of the zero cross points) of the reference burst signal BCOSC.
In the circuit arrangement of FIG. 4, before the APC operation is carried out by the phase comparing circuit 15 and the APC releasing level detecting circuit 18, the adjustment is performed such that the trailing phase of the timer output MODH approaches the stable point. More particularly, the adjusting mode signal ADJ is supplied through the OR circuit 23 to the switching circuit 17 to close the switching circuit 17, whereby the phase error output holding capacitor 22 of the phase comparing circuit 15 is discharged through the switching circuit 17 to ground potential so that the count time control signal of ground level is supplied to the first monostable-multivibrator 14A of the timer circuit 14. At that time, the first monostable-multivibrator 14A is controlled to the count time of the lock-in operation mode.
Under this state, the count time of the second monostable-multivibrator 14B is adjusted by adjusting the count time adjusting element 14C and the count time of the second monostable-multivibrator 14B is adjusted until the display element 26 lights up. As a result, if the display element 26 lights up, it can be presumed that the phase of the trailing edge of the timer output MODH produced in this adjusting operation approaches very closely the stable point to be locked in the stable points of the reference burst signal BCOSC.
If the display element 26 lights up, the adjusting mode signal ADJ is switched to the normal operation mode that is indicated by logic "0" and then the circuit is switched to the APC operation mode that is to be made by the phase comparing circuit 15 and the APC releasing level detecting circuit 18. At that time, it can be considered that according to this APC operation, since the timer output MODH is adjusted to lie substantially near the stable point of the reference burst signal BCOSC, the timer output MODH can easily be locked in the stable point.
However, the prior art circuit arrangement of FIG. 4 has the following problems.
When the switching circuit 17 is opened after the adjusting operation is carried out by the adjusting mode signal ADJ, the phase of the timer output MODH is locked in the stable point of the reference burst signal BCOSC by the APC operation, so that the display element 26 maintains its lit state. However, in practice, if under this state the phase of the reference burst signal BCOSC is displaced relative to the phase of the reproduced burst signal BURST (FIG. 1) by the temperature characteristic of each circuit and the like, since the timer output MODH serves to perform the APC operation, the display element 26 keeps lighting up and hence the phase displacement can not be detected. Accordingly, it is not possible to surely obtain the reproducibility of the phase by the circuit arrangement of FIG. 4. To remove this defect, a very complicated circuit arrangement; which can remove this defect, is required in addition to the APC loop.
Secondly, if the window of the window detecting circuit 25 is not made narrow the phase can not be adjusted accurately. However, if the window of the window detecting circuit 25 is made narrow as above, it becomes very difficult to carry out the adjusting operation by using the count time adjusting element 14C in practice.
Thirdly, since there is provided the window detecting circuit 25 as the phase comparing means in addition to the phase comparing circuit 15 forming the APC loop, if the displacement of temperature characteristic and secular variation occur in the comparing circuit 15 and the window detecting circuit 25, such displacement will lead to adjusting error directly.